Integrated circuit (IC) electronic packaging technologies can include components such as semiconductor interposers that have surface wiring features. The components such as semiconductor interposers are used to interconnect one or more IC devices into functional assemblies and the surface wiring features provide the interconnecting wiring between the one or more IC devices. The surface wiring features are often constructed in multi-layered structure similar to the back-end-of-the-line wiring layers in an IC device.
The surface wiring features also includes a plurality of functional micro bumps (μbumps) that are provided in an array to which the IC devices can be joined. The functional μbumps can be in the form of an array of Cu based metal pads on each of which a solder bump is formed to provide an array of solder bumps for joining an IC device thereto. The μbumps also can be in the form of an array of Cu posts (a.k.a. Cu columns). The tops of the Cu posts are finished with a layer of solder for joining an IC device thereto.
In many 3D-IC process, aluminum or aluminum-based electrical test pads connected to the functional μbumps are formed of a different metal, such as, copper, copper-based alloy, or solder (e.g. Sn—Ag, Sn—Ag—Cu, etc.). Because the electrical test pads and the functional μbumps are formed of different metals, the chemical potential between the two metals drive a galvanic process when the electrical test pads and the functional μbumps are exposed to wet chemical processes with solutions having low resistivity.
Referring to FIG. 1, an example of a surface metal structure having two different metals on an electronic packaging structure 10 will be used to describe galvanic effect. FIG. 1 shows a functional metal feature 2 made of a first metal and an electrical test pad 3 made of a second metal provided on a substrate 10 of an IC device. The functional metal feature 2 can be the functional μbumps mentioned above. In the illustrated example, the functional metal feature 2 is made primarily of copper and the electrical test pad 3 is made of aluminum. The functional μbump 2 and the electrical test pad 3 are electrically connected to each other by their respective wiring features 2W and 3W and vias 70. The standard reduction potential E0 of aluminum is 1.66V compared to the E0 of copper, which is −0.34V. This difference in the reduction potential between the two metals drive a galvanic process expressed byAl+ 3/2Cu2+(aq)→Al3+(aq)+ 3/2Cu E0=2VWhen the Al electrical test pads and the Cu functional μbumps are exposed to wet chemical processes with solutions having low resistivity, the aqueous electrolyte in the solution and the internal wiring in the substrate 10 that connects the Al test pad 3 and the Cu μbump 2 completes a circuit and form a galvanic cell. A cathodic reaction (reduction) takes place at the Al test pad 3 and an anodic reaction (oxidation) takes place at the Cu μbump 2. The anodic reaction, M2++2e−→M, results in deposition of impurity metal particles (mostly Al metal dissolved in the aqueous solution from the cathodic reaction and/or formed a oxidation layer) at the Cu μbump 2 which is not desired because such impurities will interfere with wetting of solder to the Cu μbump 2 in subsequent processes.
Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) metal layer is often used to provide a surface finishing layer over the functional μbumps during assembly processes. Precious metals as Gold, Silver and Palladium have very good properties on durability and chemical resistance.
The ENEPIG surface finishing process is one kind of electroless plating technology that does not require photolithographic process. However, it now faces a problem for 3D-IC package process. Because photolithographic process is used to protect the non-process areas such as aluminum pads in some embodiment, photoresist will leach out at high temperature during the ENEPIG surface fishing process. The resulting residual photoresist are sources of contamination for the chemicals used in the subsequent wet chemical process. For example, the photoresist can contaminate a plating bath shortening the plating bath life and also can redeposit on functional copper metal features resulting in defects that lowers the product yield. This results in higher cost for the 3D-IC manufacturing process. The ENEPIG surface finishing is an exemplary process that illustrate the galvanic damage in some specific embodiments of 3D-IC integrated package process, and do not limit the scope of the embodiments of electroless plating technology. Generally, those packaging processes that can provide an external conducting path may suffer galvanic damage.
The drawing figures are schematic illustrations and they are not intended to provide precise dimensions.